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1 ? ISL8105, ISL8105a +5v or +12v single-phase synchronous buck converter pwm controller with integrated mosfet gate drivers the ISL8105, ISL8105a is a simple single-phase pwm controller for a synchronous buck converter. it operates from +5v or +12v bias supply voltage. with integrated linear regulator, boot diode, and n-channel mosfet gate drivers, the ISL8105, ISL8105a reduces ex ternal component count and board space requirements. these make the ic suitable for a wide range of applications. utilizing voltage-mode control, the output voltage can be precisely regulated to as low as 0.6v. the 0.6v internal reference features a maximum tolerance of 1.0% over the commercial temperature range, and 1.5% over the industrial temperature range. two fixed oscillator frequency versions are available; 300khz (ISL8105 for high efficiency applications) and 600khz (is l8105a for fast transient applications). the ISL8105, ISL8105a features the capability of safe start-up with pre-biased load. it also provides overcurrent protection by monitoring the on-resistance of the bottom-side mosfet to inhibit pwm operation appropriately. during start-up interval, the resistor connected to bgate/bsoc pin is employed to program overcurrent protection condition. this approach simplifies the implementation and does not deteriorate converter efficiency. pinouts features ? operates from +5v or +12v bias supply voltage - 1.0v to 12v input voltage range (up to 20v possible with restrictions; see ?input voltage considerations? on page 9) - 0.6v to v in output voltage range ? 0.6v internal reference voltage - 1.0% tolerance over the commercial temperature range (0c to +70c) - 1.5% tolerance over the industrial temperature range (-40c to +85c). ? integrated mosfet gate dr ivers that operate from v bias (+5v to +12v) - bootstrapped high-side gate driver with integrated boot diode - drives n-channel mosfets ? simple voltage-mode pwm control - traditional dual edge modulation ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty cycle ? fixed operating frequency - 300khz for ISL8105 - 600khz for ISL8105a ? fixed internal soft-start with pre-biased load capability ? lossless, programmable overcurrent protection - uses bottom-side mosfet?s r ds(on) ? enable/disable function using comp/en pin ? output current sourcing and sinking currents ? pb-free (rohs compliant) applications ? 5v or 12v dc/dc regulators ? industrial power systems ? telecom and datacom applications ? test and measurement instruments ? distributed dc/dc power architecture ? point of load modules ISL8105, ISL8105a (10 ld 3x3 dfn) top view ISL8105, ISL8105a (8 ld soic) top view boot tgate n/c gnd bgate/bsoc lx comp/en fb n/c vbias 2 3 4 1 5 9 8 7 10 6 gnd lx comp/en fb vbias boot tgate gnd bgate/bsoc 2 3 4 1 5 8 7 6 data sheet april 15, 2010 fn6306.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6306.5 april 15, 2010 typical application diagram ordering information part number (note) part marking switching frequency (khz) temperature range (c) package (pb-free) pkg. dwg. # ISL8105crz* 5crz 300 0 to +70 10 ld dfn l10.3x3c ISL8105ibz* 8105 ibz 300 -40 to +85 8 ld soic m8.15 ISL8105irz* 5irz 300 -40 to +85 10 ld dfn l10.3x3c ISL8105acrz* 05az 600 0 to +70 10 ld dfn l10.3x3c ISL8105aibz* 8105 aibz 600 -40 to +85 8 ld soic m8.15 ISL8105airz* 5aiz 600 -40 to +85 10 ld dfn l10.3x3c ISL8105aeval1z evaluation board *add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. q1 q2 l out c out r 0 ISL8105 r 1 r 2 v out c dcpl r bsoc tgate lx bgate/bsoc boot c 1 c 2 c 3 r 3 comp/en fb gnd c boot c bulk c hf v in +1v to +12v v bias +5v or +12v vbias ISL8105, ISL8105a
3 fn6306.5 april 15, 2010 ISL8105, ISL8105a block diagram + - + - + - oscillator inhibit pwm comparator error amp vbias pwm gnd fb comp/en oc comparator gate control logic boot tgate lx 21.5 a bgate/bsoc v bias soft-start por and sample and hold d boot + - dis 0.4v internal regulator dis 0.6v to bgate/bsoc 20 a 20k 5v int. 5v int. fixed 300khz or 600khz
4 fn6306.5 april 15, 2010 absolute maximum rati ngs thermal information bias voltage, v bias . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +15.0v boot voltage, v boot . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +36.0v tgate voltage, v tgate . . . . . . . . . . . v lx - 0.3v to v boot + 0.3v bgate/bsoc voltage, v bgate/bsoc . .gnd - 0.3 to v bias + 0.3v lx voltage, v lx . . . . . . . . . . . . . . . . . .gnd - 0.3v to v boot + 0.3v upper driver supply voltage, v boot - v lx . . . . . . . . . . . . . . . .15v clamp voltage, v boot - v bias . . . . . . . . . . . . . . . . . . . . . . . . . .24v fb, comp/en voltage . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6v thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 95 n/a dfn package (notes 1, 2) . . . . . . . . . . 44 5.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions bias voltage, v bias . . . . . +5v 10%, +12v 20%, or 6.5v to 14.4v ambient temperature range ISL8105c, ISL8105ac . . . . . . . . . . . . . . . . . . . . . . 0c to +70c ISL8105i, ISL8105ai. . . . . . . . . . . . . . . . . . . . . . .-40c to +85c junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposur e to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise no ted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter symbol test conditions min typ max units input supply currents shutdown v bias supply current i vbias_s v bias = 12v; disabled 4 5.2 7 ma disable disable threshold (comp/en pin) v disable 0.375 0.4 0.425 v oscillator nominal frequency range f osc ISL8105c 270 300 330 khz ISL8105i 240 300 330 khz f osc ISL8105ac 540 600 660 khz ISL8105ai 510 600 660 khz ramp amplitude (note 3) v osc 1.5 v p-p power-on reset rising v bias threshold v por_r 3.9 4.1 4.3 v v bias por threshold hysteresis v por_h 0.30 0.35 0.40 v reference nominal reference voltage v ref 0.6 v reference voltage tolerance ISL8105c (0c to +70c) -1.0 +1.0 % ISL8105i (-40c to +85c) -1.5 +1.5 % error amplifier dc gain (note 3) gain dc 96 db unity gain-bandwidth (note 3) ugbw 20 mhz slew rate (note 3) sr 9 v/s gate drivers tgate source resistance r tg-srch v bias = 14.5v, 50ma source current 3.0 ISL8105, ISL8105a
5 fn6306.5 april 15, 2010 functional pin descr iption (soic, dfn) boot (soic pin 1, dfn pin 1) this pin provides ground refe renced bias voltage to the top-side mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive an n-channel mosfet (equal to v bias minus the on-chip boot diode voltage drop), with respect to lx. tgate (soic pin 2, dfn pin 2) connect this pin to the gate of top-side mosfet; it provides the pwm-controlled gate drive. it is also monitored by the adaptive shoot-throug h protection circuitry to determine when the top-side mosfet has turned off. gnd (soic pin 3, dfn pin 4) this pin represents the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. bgate/bsoc (soic pin 4, dfn pin 5) connect this pin to the gate of the bottom-side mosfet; it provides the pwm-controlled gate drive (from v bias ). this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turned off. during a short period of time following power-on reset (por) or shut-down release, this pin is also used to determine the current limit threshold of the converter. connect a resistor (r bsoc ) from this pin to gnd. see ?overcurrent protection (ocp)? on page 7 for equations. an overcurrent trip cycles the so ft-start function, after two dummy soft-start time-outs. so me of the text describing the bgate function may leave off the bsoc part of the name, when it is not relevant to the discussion. vbias (soic pin 5, dfn pin 6) this pin provides the bias supply for the ISL8105, as well as the bottom-side mosfet's gate and the boot voltage for the top-side mosfet's gate. an internal 5v regulator will supply bias if v bias rises above 6.5v (but the bgate/bsoc and boot will still be sourced by v bias ). connect a well decoupled +5v or +12v supply to this pin. fb (soic pin 6, dfn pin 8) this pin is the inverting input of the internal error amplifier. use fb, in combination wit h the comp/en pin, to compensate the voltage-cont rol feedback loop of the converter. a resistor divider fr om the output to gnd is used to set the regulation voltage. comp/en (soic pin 7, dfn pin 9) this is a multiplexed pin. during soft-start and normal converter operation, this pin represents the output of the error amplifier. use comp/en, in combination wi th the fb pin, to compensate the voltage-control feedback loop of the converter. pulling comp/en low (v disable = 0.4v nominal) will disable (shut-down) the cont roller, which causes the oscillator to stop, the bgate and tgate outputs to be held low, and the soft-start circui try to re-arm. the external pull-down device will initially need to overcome maximum of 5ma of comp/en output current. however, once the ic is disabled, the comp output will also be disabled, so only a 20a current source will continue to draw current. when the pull-down device is released, the comp/en pin will start to rise at a rate determined by the 20a charging up the capacitance on the comp/en pin. when the comp/en pin rises above the v disable trip point, the ISL8105 will begin a new initialization and soft-start cycle. tgate source resistance r tg-srcl v bias = 4.25v, 50ma source current 3.5 tgate sink resistance r tg-snkh v bias = 14.5v, 50ma source current 2.7 tgate sink resistance r tg-snkl v bias = 4.25v, 50ma source current 2.7 bgate source resistance r bg-srch v bias = 14.5v, 50ma source current 2.4 bgate source resistance r bg-srcl v bias = 4.25v, 50ma source current 2.75 bgate sink resistance r bg-snkh v bias = 14.5v, 50ma source current 2.0 bgate sink resistance r bg-snkl v bias = 4.25v, 50ma source current 2.1 overcurrent protection (ocp) bsoc current source i bsoc ISL8105c; bgate/bsoc disabled 19.5 21.5 23.5 a ISL8105i; bgate/bsoc disabled 18.0 21.5 23.5 a note: 3. limits established by characterization and are not production tested. electrical specifications recommended operating conditions, unless otherwise no ted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units ISL8105, ISL8105a
6 fn6306.5 april 15, 2010 ISL8105, ISL8105a lx (soic pin 8, dfn pin 10) connect this pin to the source of the top-side mosfet and the drain of the bottom-side mosfet. it is used as the sink for the tgate driver and to monitor the voltage drop across the bottom-side mosfet for overcurrent protection. this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the top-side mosfet has turned off. n/c (dfn only; pin3, pin 7) these two pins in the dfn package are no connect. functional description initialization (por and ocp sampling) figure 1 shows a start-up waveform of ISL8105. the power-on-reset (por) function continually monitors the bias voltage at the vbias pin. once the rising por threshold is exceeded 4v (v por nominal), the por function initiates the overcurrent protection (ocp) sample and hold operation (while comp/en is ~1v). when the sampling is complete, v out begins the soft-start ramp. if the comp/en pin is hel d low during power-up, the initialization will be delayed unt il the comp/en is released and its voltage rises above the v disable trip point. figure 2 shows a typical power-up sequence in more detail. the initialization starts at t 0 , when either v bias rises above v por , or the comp/en pin is released (after por). the comp/en will be pulled up by an internal 20a current source, but the timing will not begin until the comp/en exceeds the v disable trip point (at t 1 ). the external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20a current source will charge the comp/en pin. with typical values, it should add a small delay compared to the soft-start times. the comp/en will continue to ramp to ~1v. from t 1 , there is a nominal 6.8ms delay, which allows the vbias pin to exceed 6.5v (if rising up towards 12v), so that the internal bias regulator can turn on cleanly. at the same time, the bgate/bsoc pin is initialized by disabling the bgate driver and drawing bsoc (nominal 21.5a) through r bsoc . this sets up a voltage that will represent the bsoc trip point. at t 2 , there is a variable time period for the ocp sample and hold operation (0ms to 3.4ms nominal; the longer time occurs with the higher overcurrent setting). the sample and hold uses a digital counter and dac to save the voltage, so the stored value does not degrade, for as long as the v bias is above v por . see ?overcurrent protection (ocp)? on page 7 for more details on the equations and variables. upon the completion of sample and hold at t 3 , the soft-start operation is initiated, and the output voltage ramps up between t 4 and t 5 . soft-start and pre-biased outputs functionally, the soft-start internally ramps the reference on the non-inverting terminal of the error amp from 0v to 0.6v in a nominal 6.8ms. the output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the v out will be less than the nominal time), due to some initialization timing, between t 3 and t 4 ). the ramp is created digitally, so there will be 64 small discrete steps. there is no simple way to change this ramp rate externally, and it is the same for either frequency version of the ic (300khz or 600khz). after an initialization period (t 3 to t 4 ), the error amplifier (comp/en pin) is enabled, and begins to regulate the converter's output voltage duri ng soft-start. the oscillator's triangular waveform is compared to the ramping error amplifier voltage. this generates lx pulses of increasing width that charge the output capacitors. when the internally generated soft-start voltage exceeds the reference voltage (0.6v), the soft-start is complete and the output should be in regulation at the expected volt age. this method provides a rapid and controlled output voltage rise; there is no large inrush current charging the output capacitors. the entire start-up sequence from por typically takes up to 17ms; up figure 1. por and soft-start operation v bias v out v comp/en ~4v por figure 2. bgate/bsoc and soft-start operation comp/en bgate/bsoc v out bgate starts switching 3.4ms 3.4ms t0 t1 t2 t3 0ms to 3.4ms t5 t4
7 fn6306.5 april 15, 2010 ISL8105, ISL8105a to 10.2ms for the delay and ocp sample and 6.8ms for the soft-start ramp. figure 3 shows the normal curve in blue; initialization begins at t 0 , and the output ramps between t 1 and t 2 . if the output is pre-biased to a voltage less t han the expected value, as shown by the red curve, the ISL8105, ISL8105a will detect that condition. neither mo sfet will turn on until the soft-start ramp voltage exceeds the output; v out starts seamlessly ramping from there. if the output is pre-biased to a voltage above the expected va lue, as in the gray curve, neither mosfet will turn on until the end of the soft-start, at which time it will pull the output voltage down to the final value. any resistive load connected to the output will help pull down the voltage (at the rc rate of the r of the load and the c of the output capacitance). if the v in for the synchronous buck converter is from a different supply that comes up after v bias , the soft-start would go through its cycle, but with no output voltage ramp. when v in turns on, the output would follow the ramp of the v in from zero up to the final expected voltage (at close to 100% duty cycle, with co mp/en pin >4v). if v in is too fast, there may be excessive inrush current charging the output capacitors (only the beginning of the ramp, from zero to v out matters here). if this is not acceptable, then consider changing the sequencing of the power supplies, or sharing the same supply, or adding sequencing logic to the comp/en pin to delay the soft-start until the v in supply is ready (see ?input voltage considerations? on page 9). if the ic is disabled after soft-start (by pulling comp/en pin low), and then enabled (by releasing the comp/en pin), then the full initialization (including ocp sample) will take place. however, there is no new ocp sampling during overcurrent retries. if the outp ut is shorted to gnd during soft-start, the ocp will handle it, as described in the next section. if the output is shorted to g nd during soft-start, the ocp will handle it, as described in the next section. overcurrent protection (ocp) the overcurrent function protects the converter from a shorted output by using the bottom-side mosfet's on-resistance, r ds(on) , to monitor the current. a resistor (r bsoc ) programs the overcurrent trip level (see ?typical application diagram? on page 2). this method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. if over current is detected, the output immediately shuts off, it cycles the soft-start function in a hiccup mode (2 dummy soft-start time-outs, then up to one real one) to provide fault prot ection. if the shorted condition is not removed, this cycle will continue indefinitely. following por (and 6.8ms delay), the ISL8105, ISL8105a initiates the overcurrent protection sample and hold operation. the bgate driver is disabled to allow an internal 21.5a current source to develop a voltage across r bsoc . the ISL8105, ISL8105a samples this voltage (which is referenced to the gnd pin) at the bgate/bsoc pin, and holds it in a counter and dac combination. this sampled voltage is held internally as the overcurrent set point, for as long as power is applied, or until a new sample is taken after coming out of a shut-down. the actual monitoring of the bottom-side mosfet's on-resistance starts 200ns ( nominal) after the edge of the internal pwm logic signal (that creates the rising external bgate signal). this is done to allow the gate transition noise and ringing on the lx pin to settle out before monitoring. the monitoring ends when the internal pwm edge (and thus bgate) goes low. the ocp can be detected anywhere within the above window. if the regulator is running at high tgate duty cycles (around 75% for 600khz or 87% for 300khz operation), then the bgate pulse width may not be wide enough for the ocp to properly sample the r ds(on) . for those cases, if the bgate is too narrow (or not there at all) for 3 consecutive pulses, then the third pulse will be stre tched and/or inserted to the 425ns minimum width. this allows for ocp monitoring every third pulse under this condition. this can introduce a small pulse-width error on the output voltage, which will be corrected on the next pulse; and the output ripple voltage will have an unusual 3-clock pattern, which may look like jitter. if the ocp is disabled (by choosing a too-high value of r bsoc , or no resistor at all), then the pulse stretching feature is also disabled. figur e 4 illustrates the bgate pulse width stretching, as the width gets smaller. figure 3. soft-start with pre-bias v out normal v out pre-biased t1 t2 t0 t1 t2 v out over-charged v out pre-biased v out normal
8 fn6306.5 april 15, 2010 the overcurrent function will tr ip at a peak inductor current (i peak ) determined by equation 1: where i bsoc is the internal bsoc current source (21.5a typical). the scale factor of 2 doubles the trip point of the mosfet voltage drop, compared to the setting on the r bsoc resistor. the oc trip poin t varies in a system mainly due to the mosfet's r ds(on) variations (over process, current and temperature). to avoid overcurrent tripping in the normal operating load range, find the r bsoc resistor from equation 1 with: 1. the maximum r ds(on) at the highest junction temperature 2. the minimum i bsoc from the specification table 3. determine i peak for i peak > i out(max) + , where is the output inductor ripple current. for an equation for the ripple current, see ?output inductor selection? on page 13 . the range of allowable voltages detected (2*i bsoc *r bsoc ) is 0mv to 475mv; but the practical range for typical mosfets is typically in the 20mv to 120mv ballpark (500 to 3000 ). if the voltage drop across r bsoc is set too low, that can cause almost continuous ocp tripping and retry. it would also be very sensitive to system noise and inrush current spikes, so it should be avoided. the maximum usable setting is around 0.2v across r bsoc (0.4v across the mosfet); values above that might disable the protection. any voltage drop across r bsoc that is greater than 0.3v (0.6v mosfet trip point) will disable the ocp. the preferred method to disable ocp is simply to remove the resistor, which will be detected as no ocp. note that conditions during power-up or during a retry may look different than normal operation. during power-up in a 12v system, the ic starts opera tion just above 4v; if the supply ramp is slow, the soft-start ramp might be over well before 12v is reached. so with bottom-side gate drive voltages, the r ds(on) of the mosfets will be higher during power-up, effectively lowering the ocp trip. in addition, the ripple current will likely be di fferent at lower input voltage. another factor is the digital nature of the soft-start ramp. on each discrete voltage step, there is in effect a small load transient, and a current spike to charge the output capacitors. the height of the current spike is not controlled; it is affected by the step size of the output, the value of the output capacitors, as well as the ic error amp compensation. so it is possible to trip the ov ercurrent with inrush current, in addition to the normal load and ripple considerations. figure 5 shows the output response during a retry of an output shorted to gnd. at time t 0 , the output has been turned off, due to sensing an overcurrent condition. there are two internal soft-start delay cycles (t 1 and t 2 ) to allow the mosfets to cool down, to keep the average power dissipation in retry at an acceptable level. at time t 2 , the output starts a normal soft-start cycle, and the output tries to ramp. if the short is still app lied, and the current reaches the bsoc trip point any time during soft-start ramp period, the output will shut off and return to time t 0 for another delay cycle. thus, the retry period is two dummy soft-start cycles plus one variable one (which depends on how long it takes to trip the sensor each time). figure 5 also shows an example where the output gets about half-way up before shutting down; therefore, the retry (or hiccup) time will be around 17ms. the minimum should be nominally 13.6ms and the maximum 20.4ms. if the short condition is finally removed, the output should ramp up normally on the next t 2 cycle. starting up into a shorted load looks the same as a retry into that same shorted load. in both cases, ocp is always enabled during soft-start; once it trips, it will go into retry (hiccup) mode. the retry cycle will always have two dummy time-outs, plus whatever fraction of the real soft-start time passes before the detection and shutoff; at that point, the logic immediately starts a new two dummy cycle time-out. figure 4. bgate pulse stretching bgate > 425ns bgate = 425ns bgate < 425ns bgate << 425ns i peak 2i bsoc r bsoc r ds on () ------------------------------------------------------ = (eq. 1) i () 2 ---------- i ISL8105, ISL8105a
9 fn6306.5 april 15, 2010 output voltage selection the output voltage can be programmed to any level between the 0.6v internal reference, up to the v bias supply. the ISL8105, ISL8105a can run at near 100% duty cycle at zero load, but the r ds(on) of the top-side mosfet will effectively limit it to something less as the load current increases. in addition, the ocp (if enabled) will also limit the maximum effective duty cycle. an external resistor divider is used to scale the output voltage relative to the internal reference voltage, and feed it back to the inverting input of the error amp. see ?typical application diagram? on page 2 for more detail; r 1 is the upper resistor; r offset (shortened to r 0 below) is the lower one. the recommended value for r 1 is 1k to 5k (1% for accuracy) and then r offset is chosen according to equations 2 and 3. since r 1 is part of the compensation circuit (see ?feedback compensation? on page 11), it is often easier to change r offset to change the output voltage; that way the compensat ion calculations do not need to be repeated. if v out = 0.6v, then r offset can be left open. output voltages less t han 0.6v are not available. input voltage considerations the ?typical application diagram? on page 2 shows a standard configuration where v bias is either 5v (10%) or 12v (20%); in each case, the gate drivers use the v bias voltage for bgate and boot/tgate. in addition, v bias is allowed to work anywhere from 6.5v up to the 14.4v maximum. the v bias range between 5.5v and 6.5v is not allowed for long-term reliability reasons, but transitions through it to voltages above 6.5v are acceptable. there is an internal 5v regulator for bias; it turns on between 5.5 and 6.5v. some of the delay after por is there to allow a typical power supply to ramp-up past 6.5v before the soft-start ramps begins. this prevents a disturbance on the output, due to the internal regulator turning on or off. if the transition is slow (not a step change), the disturbance should be minimal. so while the recommendation is to not have the output enabled during the transition through this region, it may be acceptable. the user should monitor the output for their application to see if there is any problem. the v in to the top-side mosfet can share the same supply as v bias but can also run off a separate supply or other sources, such as outputs of other regulators. if v bias powers up first, and the v in is not present by the time the initialization is done, then the soft-start will not be able to ramp the output, and the output will later follow part of the v in ramp when it is applied. if this is not desired, then change the sequencing of t he supplies, or use the comp/en pin to disable v out until both supplies are ready. figure 6 shows a simple sequencer for this situation. if v bias powers up first, q 1 will be off, and r 3 pulling to v bias will turn q 2 on, keeping the ISL8105, ISL8105a in shutdown. when v in turns on, the resistor divider r 1 and r 2 determines when q 1 turns on, which will turn off q 2 and release the shut-down. if v in powers up first, q 1 will be on, turning q 2 off; so the ISL8105, ISL8105a will start-up as soon as v bias comes up. the v disable trip point is 0.4v nominal, so a wide variety of nfet's or npn's or even some logic ic's can be used as q1 or q 2 ; but q 2 must be low leakage when off (open-drain or open-collector) so as not to interfere with the comp output. q 2 should also be placed near the comp/en pin. the v in range can be as low as ~1v (for v out as low as the 0.6v reference). it can be as high as 20v (for v out just below v in ). there are some restrictions for running high v in voltage. the first consideration for high v in is the maximum boot voltage of 36v. the v in (as seen on lx) + v bias (boot voltage - the diode drop) + any ringing (or other transients) on the boot pin must be less than 36v. if v in is 20v, that limits v bias + ringing to 16v. the second consideration for high v in is the maximum (boot - v bias ) voltage; this must be less than 24v. since boot = v in + v bias + ringing, that reduces to (v in + ringing) figure 5. overcurrent retry operation 6.8ms v out 0ms to 6.8ms t1 t2 t0 t1 t2 6.8ms 6.8ms internal soft-start ramp v out 0.6v r 1 r 0 + () r 0 ------------------------- - ? = (eq. 2) r 0 r 1 0.6v ? v out 0.6v ? ---------------------------------- = (eq. 3) figure 6. sequencer circuit r 2 v in r 1 r 3 v bias to comp/en q 2 q 1 ISL8105, ISL8105a
10 fn6306.5 april 15, 2010 must be <24v. so based on typical circuits, a 20v maximum v in is a good starting assumption; the user should verify the ringing in their particular application. another consideration for high v in is duty cycle. very low duty cycles (such as 20v in to 1.0v out, for 5% duty cycle) require component selection co mpatible with that choice (such as low r ds(on) bottom-side mosfet, and a good lc output filter). at t he other extreme (for example, 20v in to 12v out), the top-side mosfet needs to be low r ds(on) . in addition, if t he duty cycle gets too high, it can affect the overcurrent sample time. in all cases, the input and output capacitors and both mosfets must be rated for the voltages present. switching frequency the switching frequency is either a fixed 300khz or 600khz, depending on the part number chosen (ISL8105 is 300khz; ISL8105a is 600khz; the generic name ?ISL8105? may apply to either in the rest of this document, except when choosing the frequency). however, all of the other timing mentioned (por delay, ocp sample, soft-start, etc.) is independent of the clock frequency (unless otherwise noted). boot refresh in the event that the tgate is on for an extended period of time, the charge on the boot capacitor can start to sag, raising the r ds(on) of the top-side mosfet. the ISL8105 has a circuit that detects a long tgate on-time (nominal 100s), and forces the bgate to go higher for one clock cycle, which will allow the boot capacitor some time to recharge. separately, the oc p circuit has a bgate pulse stretcher (to be sure the sample time is long enough), which can also help refresh the boot. but if ocp is disabled (no current sense resistor), the r egular boot refresh circuit will still be active. current sinking the ISL8105 incorporates a mosfet shoot-through protection method which allows a converter to sink current as well as source current. care should be exercised when designing a converter with the ISL8105 when it is known that the converter may sink current. when the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. this means that the converter is boosting current into the v in rail. if there is nowhere for this current to go, such as to other distributed loads on the v in rail, through a voltage limiting protection device, or other methods, the capacitance on the v in bus will absorb the current. this situation will allow voltage level of the v in rail (also lx) to increase. if the voltage level of the lx is increased to a level that exceeds the maximum voltage rating of the ISL8105, then the ic will experience an irreversible failure and the converter will no longer be operational. ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. application guidelines layout considerations as in any high-frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 7 shows the critical power components of the converter. to minimize the voltage overshoot/undershoot, the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 8 should be located as close together as possible. please note that the capacitors c in and c o each represent numerous physical capacitors. locate the ISL8105 within three inches of the mosfets, q 1 and q 2 . the circuit traces for the mosfets? gate and source connections from the ISL8105 must be sized to handle up to 1a peak current. proper grounding of the ic is important for correct operation in noisy environments. the gnd pin should be connected to a large copper fill under th e ic which is subsequently connected to board ground at a quiet location on the board, typically found at an input or output bulk (electrolytic) capacitor. figure 8 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. locate the resistor, r bsoc , close to the bgate/bsoc pin as the internal bsoc current source is only 21.5a. pgnd l o c o bgate tgate lx q1 q2 figure 7. printed circuit board power and ground planes or islands v in v out return ISL8105 c in load ISL8105, ISL8105a
11 fn6306.5 april 15, 2010 minimize the loop from any pulldown transistor connected to comp/en pin to reduce antenna effect. provide local decoupling between vbias and gnd pins as described earlier. locate the capacitor, c boot , as close as practical to the boot and lx pins. all components used for feedback compensation (not shown) should be located as close to the ic as practical. feedback compensation this section highlights the design considerations for a voltage-mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 9). figure 9 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the ISL8105 circuit. the output voltage (v out ) is regulated to the reference voltage, v ref , level. the error amplifier output (comp pin voltage) is compar ed with the oscillator (osc) triangle wave to provide a pulse-width modulated wave with an amplitude of v in at the lx node. the pwm wave is smoothed by the outpu t filter (l and c). the output filter capacitor bank?s equivalent series resistance is represented by the series resistor esr. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by th e output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, c and esr represent the total output capacitance and its equivalent series resistance. the compensation network consists of the error amplifier (internal to the ISL8105) and the external r 1 to r 3 , c 1 to c 3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than +45). phase margin is the differ ence between the closed loop phase at f 0db and +180. equations 5 through 8 that rela te the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 9. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k to 10k , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). if setting the output voltage to be equal to the reference set voltage as shown in figure 9, the design procedure can be followed as presented in equation 5. 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher t he quality factor of the output filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the regulator?s switching frequency. change the numerical factor to reflect desired placement of this pole. placement of f p2 lower in figure 8. printed circuit board small signal layout guidelines +v bias ISL8105 bgate/bsoc gnd v bias boot l o c o v out load q1 q2 lx +v in c boot c vbias r bsoc gnd f lc 1 2 lc ? ? --------------------------- = f ce 1 2 c esr ?? --------------------------------- = (eq. 4) figure 9. voltage-mode buck converter compensation design - + e/a vref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator esr external circuit ISL8105 v out v osc dcr tgate lx bgate r 2 v osc r 1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 5) c 1 1 2 r 2 0.5 f lc ?? ? ---------------------------------------------- - = (eq. 6) c 2 c 1 2 r 2 c 1 f ce 1 ? ??? -------------------------------------------------------- = (eq. 7) ISL8105, ISL8105a
12 fn6306.5 april 15, 2010 frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended that a mathemat ical model is used to plot the loop response. check the loop gain against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. the equations in equation 9, describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): compensation break frequency equations figure 10 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak dependent on the quality factor (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 10 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phase margin greater than +45. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or e xceeding half the switching frequency. when designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. t he filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern microprocessors produc e transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. for example, intel recommends that the high frequency decoupling for the pentium pro be composed of at least forty (40) 1.0mf ceramic capacitors in the 1206 surface-mount package. follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. use only specialized low-es r capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr avai lable in larger case sizes. r 3 r 1 f sw f lc ---------- - 1 ? -------------------- = c 3 1 2 r 3 0.7 f sw ?? ? ---------------------------------------------- - = (eq. 8) g mod f () d max v in ? v osc ----------------------------- - 1sf () esr c ?? + 1sf () esr dcr + () c ?? s 2 f () lc ?? ++ ----------------------------------------------------------------------------------------------------------- ? = g fb f () 1sf () r 2 c 1 ?? + sf () r 1 c 1 c 2 + () ?? ---------------------------------------------------- ? = 1sf () r 1 r 3 + () c 3 ?? + 1sf () r 3 c 3 ?? + () 1sf () r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? ------------------------------------------------------------------------------------------------------------------------- g cl f () g mod f () g fb f () ? = where s f () , 2 fj ?? = (eq. 9 ) f z1 1 2 r 2 c 1 ?? ------------------------------ - = f z2 1 2 r 1 r 3 + () c 3 ?? ------------------------------------------------- = f p1 1 2 r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? -------------------------------------------- - = f p2 1 2 r 3 c 3 ?? ------------------------------ - = (eq. 10) 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 10. asymptotic bode plot of converter gain closed loop gain 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl 20 d max v ? in v osc --------------------------------- log ISL8105, ISL8105a
13 fn6306.5 april 15, 2010 however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to hi gh slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by equation 11: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fa st control loop design, the ISL8105 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. equation 12 gives the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step t rise is the response time to the application of load t fall is the response time to the removal of load with a lower input source such as 1.8v or 3.3v, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. be sure to check bot h of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and a voltage rating of 1.5x is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately as shown in equation 13.. for a through-hole design, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series, available from avx, and the 593d, available series from sprague, are both surge current tested. mosfet selection/considerations the ISL8105 requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss v out = i x esr i = v in - v out f s x l ------------------------------- - v out v in --------------- - ? (eq. 11) t fall l o i tran v out ------------------------------ - = t rise l o i tran v in v out ? ------------------------------- - = (eq. 12) i in rms , k icm i o ? = i in rms , i o 2 dd 2 ? () i 2 12 -------- d + = or d v o vin ---------- = (eq. 13) figure 11. input-capacitor current multiplier for single-phase buck converter 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 k icm duty cycle (d) 0.5io i = 0io 0.25io ISL8105, ISL8105a
14 fn6306.5 april 15, 2010 components: conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the top and the bottom-side mosfets. these losses are distributed between the two mosfets according to duty factor. the switching losses seen when sourcing current will be different from the switching losses seen when sinking current. when sourcing current, the top-side mosfet realizes most of the switching losses. the bottom-side switch realizes mo st of the switching losses when the converter is sinking current (see equation 14). these equations assume linear voltage current transitions and do not adequately model power loss due to the reverse recovery of the upper and lower mosfet?s body diode. the gate-charge losses are dissipated by the ISL8105 and do not heat the mosfets. however, large gate charge increases the switching interval, t sw , which increases the mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. where: d is the duty cycle = v out /v in , t sw is the combined switch on and off time, and f s is the switching frequency. when operating with a 12v power supply for v bias (or down to a minimum supply voltage of 6.5v), a wide variety of nmosfets can be used. check the absolute maximum v gs rating for both mosfets; it needs to be above the highest v bias voltage allowed in t he system; that usually means a 20v v gs rating (which typically correlates with a 30v v ds maximum rating). low threshold transistors (around 1v or below) are not recommended for the reasons explained in the next paragraph. for 5v-only operation, given the reduced available gate bias voltage (5v), logic-level transistors should be used for both n-mosfets. look for r ds(on) ratings at 4.5v. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot-through protection present aboard the ISL8105 may be circumvented by these mosfets if they have large parasitic impedances and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50ns or so. bootstrap considerations figure 12 shows the top-side gate drive (boot pin) supplied by a bootstrap circuit from v bias . the boot capacitor, c boot , develops a floating supply voltage referenced to the lx pin. the supply is refreshed to a voltage of v bias less the boot diode drop (v d ) each time the lower mosfet, q 2 , turns on. check that the voltage rating of the capacitor is above the maximum v bias voltage in the system. a 16v rating should be suffic ient for a 12v system . a value of 0.1f is typical for many systems driving single mosfets. if v bias is 12v, but v in is lower (such as 5v), then another option is to connect the boot pin to 12v and remove the boot capacitor (although, you may want to add a local capacitor from boot to gnd). this will make the tgate v gs voltage equal to (12v - 5v = 7v). that should be high enough to drive most mosfets, and low enough to improve the efficiency slightly. do not leave the boot pin open, and try to get the same effect by driving boot through v bias and the internal diode; this path is not designed for the high current pulses that will result. for low v bias voltage applications where efficiency is very important, an external boot diode (in parallel with the internal one) may be considered. the external diode drop has to be lower than the internal one. the resulting higher v g-s of the top-side fet will lower its r ds(on) . the modest gain in efficiency should be balanced against the extra cost and area of the external diode. for information on the application circuit, including a complete bill-of-materials and circuit board description, can be found in application note an1258. http://www.intersil. com/data/an/an1258.pdf p bottom = io 2 x r ds(on) x (1 - d) losses while sourcing current losses while sinking current p bottom io 2 r ds on () 1d ? () 1 2 -- - io ? v in t sw f s + = p top io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = p top = io 2 x r ds(on) x d (eq. 14) p top io 2 r ds on () d 1 2 -- - io ? v in t sw + = +v bias ISL8105 gnd bgate tgate boot +1v to +12v figure 12. upper gate drive - bootstrap option v g-s v bias - v d note: v g-s v bias c boot q1 q2 +v bias + - v d + - lx ISL8105, ISL8105a
15 fn6306.5 april 15, 2010 ISL8105, ISL8105a dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 9 l m l10.3x3c 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.85 0.90 0.95 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 3.00 bsc - d2 2.33 2.38 2.43 7, 8 e 3.00 bsc - e2 1.59 1.64 1.69 7, 8 e 0.50 bsc - k0.20 - - - l 0.35 0.40 0.45 8 n102 nd 5 3 rev. 1 4/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6306.5 april 15, 2010 ISL8105, ISL8105a small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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